Top and bottom sides should be flat-ground to 0.8 um roughness or better, and free of foreign material. Optical polishing is not required.

Yes. Dopant concentration does not affect performance — the scanner delivers consistent results for all SiC grades.

No. Transparency does not affect performance — the scanner delivers consistent results for all SiC grades.

The main ones are:

1. Early non-destructive quality sorting
Rapid scanning enables pre-wafering quality binning. Low-value pucks can be discarded early, while high-grade continue for futher processing.

2. Defect-aware downstream processing
When XYZ defect coordinates are known, wafer quality can be predicted before slicing. Operators can simulate wafering outcome and apply automated routines, such as Smart Wafering™, to optimize processing strategies. It reduces scrap and maximizes defect-free wafer output — without growing more crystals.

3. Optimized laser cutting
As laser slicing becomes more common, defect maps help skip defective regions and process only high-quality zones.

4. Closed-loop crystal growth feedback
3D defect maps give crystal growth engineers fast, objective feedback. They can test process adjustments more rapidly and measure which changes truly deliver improvements.

About 1h 20m for a 6” puck, and ~2h for an 8” puck.

Yes. The scanner automatically:

– Aligns and scans the puck volume
– Processes raw data into 3D maps in real time during scanning
– Generates YieldPro™ 3D file and PDF inspection report

In the base configuration, the puck loading is manual. Automated loading can be added on request.

Operators can adjust grading protocols in accordance with their internal quality standards.

Detected defects can be sorted and filtered by location (XYZ coordinates) and size.
For example, the operator can hide small defects below a chosen threshold or exclude those near the puck edge.

Regarding defect type, the scanner’s main purpose is to reveal and quantify all internal defects rather than fully classify them. The scanner detects polytypes, micropipes, inclusions, voids, and high-density dislocation fields.

We are not aware of any other dedicated SiC puck scanners. Today, most pucks are evaluated indirectly — by splitting a sister wafer and etching it, typically with KOH.
In contrast, the SiC Puck Scanner provides a non-destructive, fast, and safe alternative. Some users even name it a “3D non-destructive etching” method.

It is important to note that puck-level and wafer-level inspections are not directly comparable, as the inspected volumes differ greatly.

In a typical wire-splitting and PL inspection workflow, around 30% of the puck volume is lost to kerfing, and only few µm below the wafer surface is analyzed by PL.  Depending on laser excitation wavelength, the probe volume can be as thick as 100um but for excitation above the bandgap it is rather 1um or below.

This means that only 2–5% of the original crystal volume is effectively inspected, compared to 100% volume coverage with the Puck Scanner. As a result, the number of detectable defects in wafers is proportionally lower.

However, defects revealed at the puck level will also be present and detectable in wafers, provided they fall within the wafer volume, and the inspection depth of PL or similar tools.

In summary, the SiC Puck Scanner offers full-volume inspection and should be compared to the current puck evaluation methods, rather than wafer-level tools.

The scanner is designed to detect defects as small as 20 µm, depending on the defect type.
Typical scans are performed with 50 µm step, which defines the positional accuracy of detected features.

This resolution is fully sufficient for puck inspection, and notably finer than typical pixel sizes in wafer-level inspection tools.

We are developing extensions of the scanning technology for AlN, GaN, and GaAs.
If you are interested in these materials, please contact us. 

We benchmarked puck-level scanning results against established post-wafering inspection tools such as SICA, Candela, and VisionTec.

For an in-depth view, check this article: What does the SiC Puck Scanner reveal?
It shows how puck-level defect maps line up with Raman and PL inspection of the produced wafers.

Yes. The YieldPro software updates are released every 2-3 months, all users are notified by email.

If scanner PC is connected to internet, the software will offer you to update automatically.

The essential hardware components are upgradable to enable futrher improvement. We will notify you of available upgrades.

• Scanner footprint (W × D × H): 1400 mm × 1400 mm × 1600 mm
• Recommended area: 3000 mm × 3000 mm (includes maintenance space)
• Weight: approx. 1000 kg
• Voltage: 200–240V 50Hz Single Phase OR 100–120V 60Hz Single Phase
• Power consumption: Max 1 kVA / Typical 400 VA
• Cooling/Water drain: Not required

No. The scanner operates fully offline.
An internet connection is only needed for downloading updates or receiving remote assistance.

SiC boules are typically crystallised by one of the two processes:

1. Sublimation method (often called “Rayleigh’s method”) that sublimates SiC powder, transports sublimated gas to the surface of the seed crystal by a heat gradient, and recrystallises it under cold temperatures. Compared with conventional Si ingots which are crystallised in the liquid phase from Si melt, the growth rate using the sublimation method is slow, making crystal defects likely to occur, and therefore requires advanced technology for crystal control.

2. High-Temperature Chemical Vapour Deposition (HTCVD). The method feeds precursor gases upwards through heating zone in vertical graphite crucible to the seed crystal placed at the top. The precursor gases are SiH₄ and a hydrocarbon. The growth temperature is ~2100–2300°C, the growth rate is 0.1-1mm/h.

Crystal growth is the most difficult step in the material value chain.The growth is mostly a blind process – there is no way to see or directly measure what is growing. As a result, compared with Silicon, SiC is a highly defective material.

Despite efforts in quality improvement the defect yield of raw crystals is still measured by double digits in average across the industry. Downstream manufacturers may not see the full weight of this problem, as defective material is filtered out earlier in the chain. But its cost is built into every SiC device.

Typical defects are micropipes and dislocations within the atomic lattice. Each defect degrades the manufacturing yield and reliability for SiC power devices. The micropipes reduce blocking voltage and gate oxide reliability. The dislocations do the same, and also reduce local carrier lifetime.

This is why detecting them at the earliest production stage is the game-changer for the industry.

SiC enables faster, cooler, and more efficient electronics — from EVs to renewables.

Among different semiconductors, the most commonly used today are industrially grown Silicon (Si) and Gallium Arsenide (GaAs). However, recently there has been a shift in the market—silicon carbide is attracting more and more investment due to its superior properties. Compared to conventional silicon-based devices, SiC offers almost 10X the breakdown field strength (2.8MV/cm vs 0.3MV/cm) and 3X the thermal conductivity, making it ideal for high-voltage applications: electric cars, power supplies, solar inverters, trains and wind turbines. Its superior conductive properties are increasingly necessary for automotive and power generation devices operating at higher voltages, higher temperatures, and higher frequencies than ever before.

Another benefit is that a SiC epitaxial layer deposited on a substrate could be much thinner, down to one-tenth of a traditional Si epitaxial layer in order to provide the same device performances. For example, the available layer thicknesses for the SiC epitaxy on SiC substrates ranges from sub-micron to more than 200µm. In comparison, this is about one-tenth of that of Si epitaxial layers.

Additionally, SiC devices reduce the amount of energy lost in a system, improve performance, reliability, and cut operating costs. For instance, in hybrid and electric vehicles SiC power solutions contribute to increased fuel economy and a larger cabin area, while in solar power generation applications they improve power loss by approximately 50%, contributing to reduced global warming.

Due to these advantages, SiC is becoming the standard material used for power electronics applications.